AMD Set to Innovate and Amaze

In news beyond the settlement of hostilities with Intel this morning, we find that AMD has announced new architectures, which, depending on what you read, is either not easily understood or fantastic if AMD can financially make it through the next year.

The Bulldozer and Bobcat architectures are showing some new things for AMD, like a work-alike to hyperthreading, to a 128bit floating point unit -

from Ars Technica

In an nutshell, AMD has taken two out-of-order back-ends and made them share a single front-end and a single floating-point/SIMD unit. Here’s how this works.

A single Bulldozer “module” looks to the OS like a single processor core with simultaneous multithreading (SMT) enabled, which makes sense, because that’s essentially what it is. But unlike a normal SMT core, instructions from each thread are dispatched, tracked throughout the execution process, and retired by a dedicated instruction window. And when instructions from one thread retire, they write their results out to a dedicated data cache (so each module has two d-caches).

AMD has not said how many instructions per cycle the front-end can dispatch, but it can’t be less than four, and it may be as high as six or eight, depending on the amount of decode hardware.

and

Right now, there isn’t enough information out there to speculate on how competitive Bulldozer and Bobcat will be with Intel’s 2011 lineup; AMD will begin doling out more details in a series of papers, starting next year. As the picture begins to get fleshed out, we’ll be able to gain a better understanding of AMD’s long-term competitive prospects.

So the Ars article shows that AMD is being very forward looking, yet for the author, not enough details  are there for a deciphering of the exact operations of the chips.

Yet if we look at AnandTech we find a slightly different take.

“A major focus is going to be improving on one of AMD’s biggest weaknesses today: heavily threaded performance. Intel addresses it with Hyper Threading, AMD is throwing a bit more hardware at the problem. The dual integer clusters you may have heard of are the route AMD is taking…”

Anand seems to have no reservations about the purpose here, or the results.

Doubling the integer resources but not the FP resources works even better when you look at AMD’s whole motivation behind Fusion. Much heavy FP work is expected to be moved to the GPU anyway, there’s little sense in duplicating FP hardware on the Bulldozer core when it will eventually have a fully capable GPU sitting on the same piece of silicon. While the first incarnation of Bulldozer, the Zambezi CPU, won’t have an on-die GPU, presumably future APUs will use the new core. In those designs the Bulldozer cores and the GPU will most likely even share the L3 cache. It’s really a very elegant design and the basis for what AMD, Intel and NVIDIA have been talking about for years now. The CPU will do what it does best while the GPU does what it is good at.

So Anand is talking about changes that will make a very effective difference on the upcoming Fusion chips, but the changes to the execution cores will be a great thing no matter what is being used for graphics. The integer performance is being increased markedly and since that is where most of the real computing takes place it is well placed.

Anand speculates that both the Bulldozer and Bobcat chips will be made on a 28nm process, which should bring them into parity with Intel, and so these chips will use less power, and should be able to be cranked up to very high frequencies – which will make for head to head competition at the least.

The AnandTech article ends with Anand telling us that things look good if the company can make it through another year. Though it is not a panacea, that 1.25 billion dollars from Intel is certainly more than a drop in a bucket.

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Quote of the day:

I have come to believe that the whole world is an enigma, a harmless enigma that is made terrible by our own mad attempt to interpret it as though it had an underlying truth. - Umberto Eco

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