Eric Bangeman from Ars Technica reports:

IBM and AMD have jointly developed a new design technique that they claim will significantly improve transistor (and overall CPU) performance. Called Dual Stress Liner (DSL), the technique cuts down on a great deal of the complexity involved with strained silicon. IBM and AMD claim transistor performance gains of nearly 24 percent using the technique. Unlike some other fabrication process improvements, the usage of DSL has not adversely impacted chip yields.

Strained silicon works by providing a layer of silicon atoms arranged in a lattice-like fashion, allowing for greater electron mobility. By using the Dual Stress Liner technique, manufacturers are able to etch away the straining materials from areas on the chip where they are not needed. DSL works on both positive (which run faster when compressed) and negative transistors (which run faster when stretched), reducing current leakage and leading to better transistor performance (and ultimately faster processors).

[Continue reading IBM, AMD Improve Strained Silicon Tech]